1. Field of the Invention
The present invention is directed to application specific integrated circuit (ASIC) designs. More specifically, but without limitation thereto, the present invention is directed to identifying and correcting timing problems in register transfer level (RTL) code for an integrated circuit design.
2. Description of the Prior Art
Previous approaches to correcting design defects in application specific integrated circuit (ASIC) designs require a significant amount of time analyzing the back-end flow, or layout, of the ASIC design. Attempting to resolve design problems at this stage in the design typically increases turnaround time (TAT) and jeopardizes schedule commitments.
Static timing analysis (STA) and timing closure are used to identify and correct timing violations in an integrated circuit design as quickly as possible to conserve valuable engineering resources and to meet production schedules. Timing violations that are identified in static timing analysis are resolved according to timing closure methods to ensure that the integrated circuit design will work in silicon according to design specifications.